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march 2007 rev 4 1/39 39 l6563 l6563a advanced transition-mode pfc controller features very precise adjustable output overvoltage protection tracking boost function protection against feedback loop failure (latched shutdown) interface for cascaded converter's pwm controller input voltage feedforward (1/v 2 ) inductor saturation detection (l6563 only) remote on/off control low ( 90a) start-up current 5ma max. quiescent current 1.5% (@ t j = 25c) internal reference voltage -600/+800 ma totem pole gate driver with active pull-down during uvlo so14 package applications pfc pre-regulators for: hi-end ac-dc adapter/charger desktop pc, server, web server iec61000-3-2 or jeida-miti compliant smps, in excess of 350w table 1. device summary part number package packaging l6563 so-14 tube l6563tr so-14 tape & reel l6563a so-14 tube l6563atr so-14 tape & reel so-14 www.st.com figure 1. block diagram + - v ref2 vb i a s ( interna l suppl y bus) + - 2.5v r1 r2 + - - + zero current detector v cc 14 123 4 zcd v cc inv comp mult cs gd 13 11 g nd 12 multipl ier r s q starter 1.7v + - 6 tbo + - 2.5v pfc_ok 7 1:1 current mirror + - run 10 0.52v 0.6v pwm_latch 8 5 vff leading-edge blanking 1:1 buffer from vff 1.4v 0.7v pwm_stop 9 vbi as uvlo c ompar ator + - 0.2v 0.26v 15 v sat disable latch uvlo 3v sat ideal diode 1 / v 2 starter off driver q tracking boost on/off control (brownout detection) line voltage feedforward inductor saturation detection ( not in l6563a ) feedback failure protection voltage regulator voltage references
contents l6563 - l6563a 2/39 contents 1 description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 1.1 pin connection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 1.2 pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 2 absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 3 thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 4 electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 5 typical electrical performance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 6 application information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 6.1 overvoltage protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 6.2 feedback failure protection (ffp) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 6.3 voltage feedforward . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 6.4 thd optimizer circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 6.5 tracking boost function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 6.6 inductor saturation detection (l6563 only) . . . . . . . . . . . . . . . . . . . . . . . . 27 6.7 power management/housekeeping functions . . . . . . . . . . . . . . . . . . . . . . 28 6.8 summary of l6563/a idle states . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 7 application examples and ideas . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 8 package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 9 revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
l6563 - l6563a description 3/39 1 description the device is a current-mode pfc controller operating in transition mode (tm). based on the core of a standard tm pfc controller, it offers improved performance and additional functions. the highly linear multiplier, along with a special correction circuit that reduces crossover distortion of the mains current, allows wide-range-mains operation with an extremely low thd even over a large load range. the output voltage is controlled by means of a voltage-mode error amplifier and a precise (1.5% @t j = 25c) internal voltage reference. th e stability of the loop and the transient response to sudden mains voltage changes are improved by the voltage feedforward function (1/v 2 correction). additionally, the ic provides the option for tracking boost operation (where the output voltage is changed tracking the mains voltage). the device features extremely low consumption ( 90 a before start-up and 5 ma running). in addition to an effective two-step ovp that handles normal operation overvoltages, the ic provides also a protection against feedback loop failures or erroneous output voltage setting. in the l6563 a protection is added to stop the pfc stage in case the boost inductor saturates. this function is not included in t he l6563a. this is the only difference between the two part numbers. an interface with the pwm co ntroller of the dc-dc conver ter supplied by the pfc pre- regulator is provided: the purpose is to stop the operation of the converter in case of anomalous conditions for the pfc stage (feedback loop failure, boost inductor's core saturation) in the l6563 only and to disable the pfc stage in case of light load for the dc- dc converter, so as to make it easier to comply with energy saving norms (blue angel, energystar, energy2000, etc.). the device includes disable functions suitable for remote on/off control both in systems where the pfc pre-regulator works as a master and in those where it works as a slave. the totem-pole output stage, capable of 600 ma source and 800 ma sink current, is suitable to drive high current mosfets or igbts. this, combined with the other features and the possibility to operate with the proprietary fixed-off-time co ntrol, makes the device an excellent low-cost solution for en61000-3-2 compliant smps in excess of 350w. figure 2. typical system block diagram v inac v outdc pwm is turned off in case of pfc?s anomalous operation for safety pfc can be turned off at light load to ease compliance with energy saving regulations. l6563 l6563a pwm or resonant controller pfc pre-regulator dc-dc converter
description l6563 - l6563a 4/39 1.1 pin connection figure 3. pin connection (top view) 1.2 pin description inv comp mult cs vff tbo pfc_ok vcc gd gnd zcd run pwm_stop pwm_latch 1 2 3 4 5 6 7 14 13 12 11 10 9 8 table 2. pin description pin n name description 1inv inverting input of the error amplifier. the in formation on the output voltage of the pfc pre- regulator is fed into the pin through a resistor divider. the pin normally features high impedance but, if the tracking boost function is used, an internal current generator programmed by tbo (pin 6) is activated. it sinks current from the pin to change the output voltage so that it tracks the mains voltage. 2comp output of the error amplifier. a compensation network is placed between this pin and inv (pin 1) to achieve stability of the voltage c ontrol loop and ensure high power factor and low thd. 3mult main input to the multiplier. this pin is co nnected to the rectified mains voltage via a resistor divider and provides the sinusoidal reference to the current loop. the voltage on this pin is used also to derive the information on the rms mains voltage. 4cs input to the pwm comparator. the current fl owing in the mosfet is sensed through a resistor, the resulting voltage is applied to th is pin and compared with an internal reference to determine mosfet?s turn-off. a second comparison level at 1.7v detects abnormal currents (e.g. due to boost inductor saturation) and, on this occurrence, shuts down the ic, reduces its consumption almost to the start-up level and asserts pwm_latch (pin 8) high. this function is not present in the l6563a. 5vff second input to the multiplier for 1/v 2 function. a capacitor and a parallel resistor must be connected from the pin to gnd. they complete the internal peak-holding circuit that derives the information on the rms mains volt age. the voltage at this pin, a dc level equal to the peak voltage at pin mult (pin 3), compensates the control loop gain dependence on the mains voltage. never connect the pin directly to gnd.
l6563 - l6563a description 5/39 6tbo tracking boost function. this pin provides a buffered vff voltage. a resistor connected between this pin and gnd defines a current that is sunk from pin inv (pin 1). in this way, the output voltage is changed proportionally to the mains voltage (tracking boost). if this function is not used leave this pin open. 7pfc_ok pfc pre-regulator output voltage monitoring/di sable function. this pin senses the output voltage of the pfc pre-regulator through a re sistor divider and is used for protection purposes. if the voltage at the pin exceeds 2.5v the ic is shut down, its consumption goes almost to the start-up level and this condition is latched. pwm_latch pin is asserted high. normal operation can be resumed only by cycl ing the vcc. this function is used for protection in case the feedback loop fails. if the voltage on this pin is brought below 0.2v the ic is s hut down and its consumption is considerably reduced. to restart the ic the volt age on the pin must go above 0.26v. if these functions are not needed, tie the pin to a voltage between 0.26 and 2.5 v. 8pwm_latch output pin for fault signaling. during normal o peration this pin features high impedance. if either a voltage above 2.5v at pfc_ok (pin 7) or a voltage above 1.7v on cs (pin 4) of l6563 is detected the pin is asserted high. norm ally, this pin is used to stop the operation of the dc-dc converter supplied by the pfc pr e-regulator by invoking a latched disable of its pwm controller. if not used, the pin will be left floating. 9pwm_stop output pin for fault signaling. during normal o peration this pin features high impedance. if the ic is disabled by a voltage below 0.5v on run (pin 10) the voltage at the pin is pulled to ground. normally, this pin is used to temporarily stop the operation of the dc-dc converter supplied by the pfc pre-regulator by disabling its pwm controller. if not used, the pin will be left floating. 10 run remote on/off control. a voltage below 0. 52v shuts down (not latched) the ic and brings its consumption to a considerably lower level. pwm_stop is asserted low. the ic restarts as the voltage at the pin goes above 0.6v. connect this pin to vff (pin 5) either directly or through a resistor divider to use this function as brownout (ac mains undervoltage) protection, tie to inv (pin 1) if the function is not used. 11 zcd boost inductor?s demagnetization sensing in put for transition-mode operation. a negative- going edge triggers mosfet?s turn-on. 12 gnd ground. current return for both the signal part of the ic and the gate driver. 13 gd gate driver output. the totem pole output stage is able to drive power mosfet?s and igbt?s with a peak current of 600 ma source and 800 ma sink. the high-level voltage of this pin is clamped at about 12v to avoid excessive gate voltages. 14 vcc supply voltage of both the signal part of the ic and the gate driver. table 2. pin description (continued) pin n name description
absolute maximum ratings l6563 - l6563a 6/39 2 absolute maximum ratings 3 thermal data table 3. absolute maximum ratings symbol pin parameter value unit v cc 14 ic supply voltage (icc = 20ma) self-limited v --- 2, 4 to 6, 8 to 10 analog inputs & outputs -0.3 to 8 v --- 1, 3, 7 max. pin voltage (i pin = 1 ma) self-limited v i pwm_stop 10 max. sink current 3 ma i zcd 9 zero current detector max. current -10 (source) 10 (sink) ma p tot power dissipation @t a = 50c 0.75 w t j junction temperature operating range -25 to 150 c t stg storage temperature -55 to 150 c table 4. thermal data symbol parameter value unit r thja maximum thermal resistance junction-ambient 120 c/w
l6563 - l6563a electrical characteristics 7/39 4 electrical characteristics table 5. electrical characteristics ( -25c < t j < +125c, v cc = 12v, c o = 1nf between pin gd and gnd, c ff =1f between pin v ff and gnd; unless otherwise specified) symbol parameter test condition min typ max unit supply voltage vcc operating range after turn-on 10.3 22 v vcc on turn-on threshold (1) 11 12 13 v vcc off turn-off threshold (1) 8.7 9.5 10.3 v hys hysteresis 2.3 2.7 v v z zener voltage icc = 20 ma 22 25 28 v supply current i start-up start-up current before turn-on, vcc = 10v 50 90 a i q quiescent current after turn-on 3 5 ma i cc operating supply current @ 70khz 3.8 5.5 ma i qdis idle state quiescent current latched by pfc_ok > vthl or vcs > v csdis 180 250 a disabled by pfc_ok < vth or run < v dis 1.5 2.2 ma i q quiescent current during static/dynamic ovp 2 3 ma multiplier input i mult input bias current v mult = 0 to 3 v -0.2 -1 a v mult linear operation range 0 to 3 v v clamp internal clamp level i mult = 1 ma 99.5 v output max. slope v mult =0 to 0.5v, v ff =0.8v v comp = upper clamp 2.2 2.34 v/v k m gain (3) v mult = 1 v, v comp = 4 v, v vff = v mult 0.375 0.45 0.525 v error amplifier v inv voltage feedback input threshold t j = 25 c 2.465 2.5 2.535 v 10.3 v < vcc < 22 v (2) 2.44 2.56 line regulation vcc = 10.3 v to 22v 2 5 mv i inv input bias current tbo open, v inv = 0 to 4 v -0.2 -1 a v cs ? v mult ? ---------------------
electrical characteristics l6563 - l6563a 8/39 symbol parameter test condition min typ max unit v invclamp internal clamp level i inv = 1 ma 99.5 v gv voltage gain open loop 60 80 db gb gain-bandwidth product 1 mhz i comp source current v comp = 4v, v inv = 2.4 v -2 -3.5 -5 ma sink current v comp = 4v, v inv = 2.6 v 2.5 4.5 ma v comp upper clamp voltage i source = 0.5 ma 5.7 6.2 6.7 v lower clamp voltage i sink = 0.5 ma (2) 2.12.252.4 v current sense comparator i cs input bias current v cs = 0 -1 a t leb leading edge blanking 100 200 300 ns td (h-l) delay to output 120 ns v csclamp current sense reference clamp v comp = upper clamp, v vff = v mult =0.5v 1.0 1.08 1.16 v vcs offset current sense offset v mult = 0, v vff = 3v 25 mv v mult = 3v, v vff = 3v 5 v csdis ic latch-off level (l6563 only) (2) 1.6 1.7 1.8 v output overvoltage i ovp dynamic ovp triggering current 17 20 23 a hys hysteresis (4) 15 a static ovp threshold (2) 2 2.15 2.3 v voltage feedforward v vff linear operation range r ff = 47 k ? to gnd 0.5 3 v ? v dropout v multpk -v vff 20 mv table 5. electrical characteristics (continued) ( -25c < t j < +125c, v cc = 12v, c o = 1nf between pin gd and gnd, c ff =1f between pin v ff and gnd; unless otherwise specified)
l6563 - l6563a electrical characteristics 9/39 symbol parameter test condition min typ max unit zero current detector v zcdh upper clamp voltage i zcd = 2.5 ma 5.0 5.7 v v zcdl lower clamp voltage i zcd = - 2.5 ma -0.3 0 0.3 v v zcda arming voltage (positive-going edge) (4) 1.4 v v zcdt triggering voltage (negative-going edge) (4) 0.7 v i zcdb input bias current v zcd = 1 to 4.5 v 1a i zcdsrc source current capability -2.5 ma i zcdsnk sink current capability 2.5 ma tracking boost function ? v dropout voltage v vff - v tbo i tbo = 0.25 ma 20 mv i tbo linear operation 0 0.25 ma i inv - i tbo current mismatch i tbo = 25 a to 0.25 ma -3.5 3.5 % v tboclamp clamp voltage v vff = 4v (2) 2.9 3 3.1 v pfc_ok v thl latch-off threshold voltage rising (2) 2.4 2.5 2.6 v v th disable threshold voltage falling (2) 0.2 v v en enable threshold voltage rising (2) 0.26 v i pfc_ok input bias current v pfc_ok = 0 to 2.5v -0.1 -1 a v clamp clamp voltage i pfc_ok = 1 ma 99.5 v pwm_latch i leak low level leakage current v pwm_latch =0 -1 a v h high level i pwm_latch = -0.5 ma 3.7 v pwm_stop i leak high level leakage current v pwm_stop = 6v 1a v l low level i pwm_stop = 0.5 ma 1v v clamp clamp voltage i pfc_ok = 2 ma 99.5 v table 5. electrical characteristics (continued) ( -25c < t j < +125c, v cc = 12v, c o = 1nf between pin gd and gnd, c ff =1f between pin v ff and gnd; unless otherwise specified)
electrical characteristics l6563 - l6563a 10/39 (1), (2) parameters tracking each other (3) the multiplier output is given by: (4) parameters guaranteed by design, functionality tested in production. symbol parameter test condition min typ max unit run function i run input bias current v run = 0 to 3 v -1 a v dis disable threshold voltage falling (2) 0.5 0.52 0.54 v v en enable threshold voltage rising (2) 0.56 0.6 0.64 v start timer t start start timer period 75 150 300 s gate driver v ohdrop dropout voltage i gdsource = 20 ma 22.6v i gdsource = 200 ma 2.5 3 v v oldrop i gdsink = 200 ma 12v t f current fall time 30 70 ns t r current rise time 40 80 ns v oclamp output clamp voltage i gdsource = 5ma; vcc = 20v 10 12 15 v uvlo saturation vcc=0 to vcc on , i sink =10ma 1.1 v table 5. electrical characteristics (continued) ( -25c < t j < +125c, v cc = 12v, c o = 1nf between pin gd and gnd, c ff =1f between pin v ff and gnd; unless otherwise specified) v cs k m v mult v comp 2.5 ? () ? v vff 2 ------------------------------------------------------------ - ? =
l6563 - l6563a typical electrical performance 11/39 5 typical electrical performance figure 4. supply current vs supply voltage figure 5. v cc zener voltage vs t j figure 6. ic consumption vs t j figure 7. feedback reference vs t j figure 8. start-up & uvlo vs t j figure 9. e/a output clamp levels vs t j vcc(v) 0 0.005 0.01 0.05 0.1 0.5 1 5 10 icc (ma) 0 5 10 15 20 co = 1nf f = 70 khz t j = 25c 25 vcc(v) 0 0.005 0.01 0.05 0.1 0.5 1 5 10 icc (ma) 0 5 10 15 20 co = 1nf f = 70 khz t j = 25c 25 tj (c) vcc z (pin 14) (v) -50 0 50 100 150 22 23 24 25 26 27 28 tj (c) vcc z (pin 14) (v) -50 0 50 100 150 22 23 24 25 26 27 28 -50 0 50 100 150 0.02 0.05 0.1 0.2 0.5 1 2 5 10 icc (ma) operating quiescent disabled or during ovp before start-up vcc = 12 v co = 1 nf f = 70 khz tj (c) latched off -50 0 50 100 150 0.02 0.05 0.1 0.2 0.5 1 2 5 10 icc (ma) operating quiescent disabled or during ovp before start-up vcc = 12 v co = 1 nf f = 70 khz tj (c) latched off v ref (v) -50 0 50 100 150 2.4 2.45 2.5 2.55 2.6 vcc = 12 v tj (c) (pin 1) v ref (v) -50 0 50 100 150 2.4 2.45 2.5 2.55 2.6 vcc = 12 v tj (c) (pin 1) tj (c) v cc-on (v) v cc-off (v) -50 0 50 100 150 9 9.5 10 10.5 11 11.5 12 12.5 tj (c) v cc-on (v) v cc-off (v) -50 0 50 100 150 9 9.5 10 10.5 11 11.5 12 12.5 tj (c) v comp (pin 2) (v) -50 0 50 100 150 1 2 3 4 5 6 7 upper clamp lower clamp vcc = 12 v tj (c) v comp (pin 2) (v) -50 0 50 100 150 1 2 3 4 5 6 7 upper clamp lower clamp vcc = 12 v
typical electrical performance l6563 - l6563a 12/39 figure 10. static ovp level vs t j figure 11. vcs clamp vs t j figure 12. dynamic ovp current vs t j (normalized value) figure 13. current-sense offset vs mains voltage phase angle figure 14. delay-to-output vs t j figure 15. ic latch-off level on current sense vs t j (l6563 only) tj (c) v comp (pin 2) (v) -50 0 50 100 150 2 2.1 2.2 2.3 2.4 2.5 vcc = 12 v tj (c) v comp (pin 2) (v) -50 0 50 100 150 2 2.1 2.2 2.3 2.4 2.5 vcc = 12 v tj (c) v csx (pin 4) (v) -50 0 50 100 150 1 1.1 1.2 1.3 1.4 1.5 vcc = 12 v v comp = upper clamp tj (c) v csx (pin 4) (v) -50 0 50 100 150 1 1.1 1.2 1.3 1.4 1.5 vcc = 12 v v comp = upper clamp i ovp -50 0 50 100 150 80% 90% 100% 110% 120% vcc = 12 v tj (c) i ovp -50 0 50 100 150 80% 90% 100% 110% 120% vcc = 12 v tj (c) ( ) v csoffset (pin 4) (mv) 0 0.628 1.256 1.884 2.512 3.14 0 5 10 15 20 25 30 vcc = 12 v tj = 25 v mult = 0 to 3v v ff = 3v v mult = 0 to 0.7v v ff = 0.7v ( ) v csoffset (pin 4) (mv) 0 0.628 1.256 1.884 2.512 3.14 0 5 10 15 20 25 30 vcc = 12 v tj = 25 v mult = 0 to 3v v ff = 3v v mult = 0 to 0.7v v ff = 0.7v tj (c) t d(h-l) (ns) -50 0 50 100 150 50 100 150 200 250 300 vcc = 12 v tj (c) t d(h-l) (ns) -50 0 50 100 150 50 100 150 200 250 300 vcc = 12 v tj (c) vpin4 (v) -50 0 50 100 150 1.0 1.2 1.4 1.6 1.8 2.0 vcc = 12 v tj (c) vpin4 (v) -50 0 50 100 150 1.0 1.2 1.4 1.6 1.8 2.0 vcc = 12 v
l6563 - l6563a typical electrical performance 13/39 figure 16. multiplier characteristics @ v ff = 1v figure 17. zcd clamp levels vs t j figure 18. multiplier characteristics @ v ff = 3v figure 19. zcd source capability vs t j figure 20. multiplier gain vs t j figure 21. vff & tbo dropouts vs t j v mult (pin 3) (v) v comp (pin 2) (v) 0 0.2 0.4 0.6 0.8 1 1.2 0 0.2 0.4 0.6 0.8 1 2.6 3.0 3.5 4.0 4.5 upper voltage clamp 5.0 5.5 v cs (pin 4) (v) vcc = 12 v tj = 25 c v mult (pin 3) (v) v comp (pin 2) (v) 0 0.2 0.4 0.6 0.8 1 1.2 0 0.2 0.4 0.6 0.8 1 2.6 3.0 3.5 4.0 4.5 upper voltage clamp 5.0 5.5 v cs (pin 4) (v) vcc = 12 v tj = 25 c tj (c) v zcd (pin 11) (v) -50 0 50 100 150 -1 0 1 2 3 4 5 6 7 vcc = 12 v i zcd = 2.5 ma upper clamp lower clamp tj (c) v zcd (pin 11) (v) -50 0 50 100 150 -1 0 1 2 3 4 5 6 7 vcc = 12 v i zcd = 2.5 ma upper clamp lower clamp v mult (pin 3) (v) v comp (pin 2) (v) 0 0.5 1 1.5 2 2.5 3 3.5 0 0.1 0.2 0.3 0.4 0.5 2.6 3.0 3.5 4.0 4.5 upper voltage clamp 5.0 5.5 v cs (pin 4) (v) vcc = 12 v tj = 25 c v mult (pin 3) (v) v comp (pin 2) (v) 0 0.5 1 1.5 2 2.5 3 3.5 0 0.1 0.2 0.3 0.4 0.5 2.6 3.0 3.5 4.0 4.5 upper voltage clamp 5.0 5.5 v cs (pin 4) (v) vcc = 12 v tj = 25 c tj (c) i zcdsrc (ma) -50 0 50 100 150 -8 -6 -4 -2 0 vcc = 12 v v zcd = lower clamp tj (c) i zcdsrc (ma) -50 0 50 100 150 -8 -6 -4 -2 0 vcc = 12 v v zcd = lower clamp k m tj (c) -50 0 50 100 150 0 0.2 0.4 0.6 0.8 1 vcc = 12 v v comp =4 v v mult = v ff =1v k m tj (c) -50 0 50 100 150 0 0.2 0.4 0.6 0.8 1 vcc = 12 v v comp =4 v v mult = v ff =1v tj (c) -50 0 50 100 150 -2 0 2 4 6 (mv) vpin5 - vpin3 vpin6 - vpin5 vcc = 12 v vpin3 = 2.9 v tj (c) -50 0 50 100 150 -2 0 2 4 6 (mv) vpin5 - vpin3 vpin6 - vpin5 vcc = 12 v vpin3 = 2.9 v
typical electrical performance l6563 - l6563a 14/39 figure 22. tbo current mismatch vs t j figure 23. run thresholds vs t j figure 24. tbo-inv current mismatch vs tbo currents figure 25. pwm_latch high saturation vs t j figure 26. tbo clamp vs t j figure 27. pwm_stop low saturation vs t j tj (c) -50 0 50 100 150 -2.4 -2.2 -2.0 -1.8 -1.6 -1.4 -1.2 -1.0 -0.8 i(inv)-i(tbo) i(inv) 100 itbo = 25 a itbo = 250 a vcc = 12 v tj (c) -50 0 50 100 150 -2.4 -2.2 -2.0 -1.8 -1.6 -1.4 -1.2 -1.0 -0.8 i(inv)-i(tbo) i(inv) 100 itbo = 25 a itbo = 250 a vcc = 12 v tj (c) vpin10 (v) -50 0 50 100 150 0.0 0.2 0.4 0.6 0.8 1.0 vcc = 12 v on off tj (c) vpin10 (v) -50 0 50 100 150 0.0 0.2 0.4 0.6 0.8 1.0 vcc = 12 v on off i(tbo) 0 100 200 300 400 500 600 -2.3 -2.2 -2.1 -2.0 -1.9 -1.8 -1.7 -1.6 vcc = 12 v tj = 25 c i(inv)-i(tbo) i(inv) 100 i(tbo) 0 100 200 300 400 500 600 -2.3 -2.2 -2.1 -2.0 -1.9 -1.8 -1.7 -1.6 vcc = 12 v tj = 25 c i(inv)-i(tbo) i(inv) 100 tj (c) vpin8 (v) -50 0 50 100 150 4.5 4.6 4.7 4.8 4.9 5.0 5.1 5.2 5.3 vcc = 12 v isource = 50 a isource = 500 a tj (c) vpin8 (v) -50 0 50 100 150 4.5 4.6 4.7 4.8 4.9 5.0 5.1 5.2 5.3 vcc = 12 v isource = 50 a isource = 500 a tj (c) -50 0 50 100 150 2.5 2.75 3 3.25 3.5 vcc = 12 v vpin3= 4 v (v) vpin6 tj (c) -50 0 50 100 150 2.5 2.75 3 3.25 3.5 vcc = 12 v vpin3= 4 v (v) vpin6 tj (c) vpin9 (v) -50 0 50 100 150 0.0 1.0 2.0 3.0 4.0 5.0 vcc = 12 v isink = 0.5 ma 0.50 0.40 0.30 0.20 0.10 0 tj (c) vpin9 (v) -50 0 50 100 150 0.0 1.0 2.0 3.0 4.0 5.0 vcc = 12 v isink = 0.5 ma 0.50 0.40 0.30 0.20 0.10 0
l6563 - l6563a typical electrical performance 15/39 figure 28. pfc_ok thresholds vs t j figure 29. uvlo saturation vs t j figure 30. start-up timer vs t j figure 31. gate-drive output low saturation figure 32. gate-drive clamp vs t j figure 33. gate-drive output high saturation tj (c) vpin7 (v) -50 0 50 100 150 0.1 0.2 0.3 0.5 1.0 2.0 3.0 vcc = 12 v on off latch-off tj (c) vpin7 (v) -50 0 50 100 150 0.1 0.2 0.3 0.5 1.0 2.0 3.0 vcc = 12 v on off latch-off tj (c) -50 0 50 100 150 0.5 0.6 0.7 0.8 0.9 1 1.1 vcc = 0 v vpin15 (v) tj (c) -50 0 50 100 150 0.5 0.6 0.7 0.8 0.9 1 1.1 vcc = 0 v vpin15 (v) tj (c) tstart (s) -50 0 50 100 150 100 110 120 130 140 150 vcc = 12 v tj (c) tstart (s) -50 0 50 100 150 100 110 120 130 140 150 vcc = 12 v v pin15 (v) 0 200 400 600 800 1,000 0 1 2 3 4 i gd (ma) tj = 25 c vcc = 11 v sink v pin15 (v) 0 200 400 600 800 1,000 0 1 2 3 4 i gd (ma) tj = 25 c vcc = 11 v sink tj (c) vpin15 clamp (v) -50 0 50 100 150 10 10.5 11 11.5 12 vcc = 20 v tj (c) vpin15 clamp (v) -50 0 50 100 150 10 10.5 11 11.5 12 vcc = 20 v 0 100 200 300 400 500 600 700 -4.5 -4 -3.5 -3 -2.5 -2 -1.5 i gd (ma) tj = 25 c vcc = 11 v source vcc - 2.0 vcc - 2.5 vcc - 3.0 vcc - 3.5 vcc - 4.0 v pin15 (v) 0 100 200 300 400 500 600 700 -4.5 -4 -3.5 -3 -2.5 -2 -1.5 i gd (ma) tj = 25 c vcc = 11 v source vcc - 2.0 vcc - 2.5 vcc - 3.0 vcc - 3.5 vcc - 4.0 v pin15 (v)
application information l6563 - l6563a 16/39 6 application information 6.1 overvoltage protection normally, the voltage control loop keeps the output voltage v o of the pfc pre-regulator close to its nominal value, set by the ratio of the resistors r1 and r2 of the output divider. neglecting the ripple components, under steady state conditions the current through r1 equals that through r2. considering that the non-inverting input of the error amplifier is internally biased at 2.5v , the voltage at pin inv w ill be 2.5v as well, then: equation 1 if the output voltage experiences an abrupt change ? vo the voltage at pin inv is kept at 2.5v by the local feedback of the error amplifier, a network connected between pins inv and comp that introduces a long time constant. then the current through r2 remains equal to 2.5/r2 but that through r1 becomes: equation 2 the difference current ? i r1 = i? r1 - i? r1 = ? v o /r1 will flow through the compensation network and enter the error amplifier (pin comp). this current is monitored inside the ic and when it reaches about 18 a the output voltage of the multiplier is forced to decrease, thus reducing the energy drawn from the mains. if the current exceeds 20 a, the ovp is triggered (dynamic ovp), and the external power transistor is switched off until the current falls approximately below 5 a. however, if the over voltage persists (e.g. in case the load is completely disconnected), the er ror amplifier will eventually satu rate low hence triggering an internal comparator (static ovp) that will keep the external power switch turned off until the output voltage comes back close to the regulated value. the output overvoltage that is able to trigger the ovp function is then: equation 3 ? v o = r1 20 10 -6 i r2 i r1 2.5 r2 ------- - v o 2.5 ? r1 --------------------- - === i ' r1 v o 2.5 ? v o ? + r1 --------------------------------------- - =
l6563 - l6563a application information 17/39 an important advantage of this technique is that the overvoltage level can be set independently of the regulated output voltage: the latter depends on the ratio of r1 to r2, the former on the individual value of r1. another advantage is the precision: the tolerance of the detection current is 15%, which means 15% tolerance on the ? v o . since it is usually much smaller than vo, the tolerance on th e absolute value will be proportionally reduced. example: v o = 400v, ? v o = 40v. then: r1 = 40v/20a = 2m ? ; r2 = 2.52m ? /(400-2.5) = 12.58k ? . the tolerance on the ovp leve l due to the l6563/a will be 400 .15 = 6 v, that is 1.36%. when either ovp is activated the quiescen t consumption is reduced to minimize the discharge of the vcc capacitor. figure 34. output voltage setting, ovp and ffp functions: internal block diagram - + 2.5v l6563 l6563a 1 2 inv comp e/a + - frequency compensation + - r2 7 pfc_ok i tbo 2.25v static ovp dynamic ovp 20 a vout { r1a r1b r1 9.5v fault (latched) tbo function r4 { r3a r3b r3 + - fault (not latched) 0.26v 9.5v
application information l6563 - l6563a 18/39 6.2 feedback failure protection (ffp) the ovp function above described is able to handle "normal" overvoltage conditions, i.e. those resulting from an abrupt load/line change or occurring at start-up. it cannot handle the overvoltage generated, for instance, when the upper resistor of the output divider (r1) fails open: the voltage loop can no longer read the information on the output voltage and will force the pfc pre-regulator to work at maximum on-time, causing the output voltage to rise with no control. a pin of the device (pfc_ok) has been dedicated to provide an additional monitoring of the output voltage with a separate resistor divider (r3 high, r4 low, see figure 34 ). this divider is selected so that the voltage at the pin reaches 2.5v if the output voltage exceeds a preset value, usually larger than the maximum vo that can be expected, also including worst-case load/line transients. example: v o = 400 v, vox = 475v. select: r3 = 3m ? ; then: r4 = 3m ? 2.5/(475-2.5) = 15.87k ? . when this function is triggered, the gate drive activity is immediately stopped, the device is shut down, its quiescent consumption is reduced below 250 a and the condition is latched as long as the supply voltage of the ic is above the uvlo threshold. at the same time the pin pwm_latch is asserted high. pwm_latch is an open source output able to deliver 3.7v min. with 0.5 ma load, intended for tripping a latched shutdown function of the pwm controller ic in the cascaded dc-dc converter, so that the entire unit is latched off. to restart the system it is necessary to recycle the input power, so that the vcc voltages of both the l6563/a and the pwm controller go below their respective uvlo thresholds. the pfc_ok pin doubles its function as a not -latched ic disable: a voltage below 0.2v will shut down the ic, reducing its consumption below 1 ma. in this case both pwm_stop and pwm_latch keep their high impedance status. to restart the ic simply let the voltage at the pin go above 0.26 v. note that this function offers a complete protection against not only feedback loop failures or erroneous settings, but also against a failure of the protection itself. either resistor of the pfc_ok divider failing short or open or a pfc_ ok pin floating will result in shutting down the ic and stopping the pre-regulator. 6.3 voltage feedforward the power stage gain of pfc pre-regulators varies with the square of the rms input voltage. so does the crossover frequency f c of the overall open-loop gain because the gain has a single pole characteristic. this le ads to large trade-offs in the design. for example, setting the gain of the error amplifier to get f c = 20 hz @ 264 vac means having f c ? 4 hz @ 88 vac, resulting in a sluggish control dynamics. additionally, the slow control loop causes large transient current flow during rapid line or load changes that are limited by the dynamics of the multiplier outpu t. this limit is consi dered when selecting the sense resistor to let the full load power pass under minimum line voltage conditions, with some margin. but a fixed current limit allows excessive power input at high line, whereas a fixed power limit requires the current limit to vary inversely with the line voltage. voltage feedforward can compensate for the gain variation with the line voltage and allow overcoming all of the above-mentioned issues. it consists of deriving a voltage proportional to the input rms voltage, feeding this voltage into a squarer/divider circuit (1/v 2 corrector) and providing the resulting signal to the multiplier that generates the current reference for the inner current control loop (see figure 35 ).
l6563 - l6563a application information 19/39 figure 35. voltage feedforward: squarer-divider (1/v 2 ) block diagram and transfer characteristic in this way a change of the line voltage will ca use an inversely propor tional change of the half sine amplitude at the output of the multiplier (if the line voltage doubles the amplitude of the multiplier output will be halved and vice versa) so that the current re ference is adapted to the new operating conditions with (ideally) no need for invoking the slow dynamics of the error amplifier. additionally, the loop gain will be constant throughout the input voltage range, which improves significantly dynamic behavior at low line an d simplifies loop design. actually, deriving a voltage proportional to the rms line voltage implies a form of integration, which has its own time constant. if it is too small the voltage generated will be affected by a considerable amount of ripple at twice the ma ins frequency that will ca use distortion of the current reference (resulting in high thd and po or pf); if it is too large there will be a considerable delay in setting the right amount of feedforward, resulting in excessive overshoot and undershoot of the pre-regulator's output voltage in response to large line voltage changes. clearly a trade-off is required. the device realizes voltage feedforward with a technique that makes use of just two external parts and that limits the feedforward time constant trade-off issue to only one direction. a capacitor c ff and a resistor r ff , both connected from the vff (pin 5) pin to ground, complete an internal peak-holding circuit that provides a dc voltage equal to the peak of the rectified sine wave applied on pin mult (pin 3). r ff provides a means to discharge c ff when the line voltage decreases (see figure 35 ). in this way, in case of sudden line voltage rise, c ff will be rapidly charged throu gh the low impedance of the internal diode and no ap preciable overshoot will be visible at the pre-regulator 's output; in case of line voltage drop c ff will be discharged with the time constant r ff c ff , which can be in the hundred ms to achieve an acceptably low steady-state ripple and have low current distortion; consequently the output voltage can experience a considerable undershoot, like in systems with no feedforward compensation. 01234 0 0.5 1 1.5 2 v ff =v mult vcsx 0.5 v comp =4v actual ideal 5 mult 3 r5 rectif ied mains r6 "ideal" diode current reference (vcsx) 9.5v vff c ff r ff e/ a o u t p u t (v comp ) - + 1/v 2 multipl ier l6563 l6563a
application information l6563 - l6563a 20/39 the twice-mains-frequency (2f l ) ripple appearing across c ff is triangular with a peak-to- peak amplitude that, with good approximation, is given by: equation 4 where f l is the line frequency. the amount of 3 rd harmonic distortion introduced by this ripple, related to the amplitude of its 2f l component, will be: equation 5 figure 36 shows a diagram that helps choose the time constant r ff c ff based on the amount of maximum desired 3 rd harmonic distortion. always connect r ff and c ff to the pin, the ic will not work properly if the pin is either left floating or connected directly to ground. figure 36. r ff c ff as a function of 3 rd harmonic distortion introduced in the input current the dynamics of the voltage feedforward input is limited downwards at 0.5v (see figure 35 ), that is the output of the mu ltiplier will not increase any mo re if the voltage on the v ff pin is below 0.5v. this helps to prevent excessive po wer flow when the line voltage is lower than the minimum specified value (brownout conditions). v ff ? 2v multpk 14f l r ff c ff + --------------------------------------- = d 3 % 100 2 f l r ff c ff --------------------------------- = d % 3 0.1 1 10 0.01 0.1 1 10 f = 50 hz l f = 60 hz l r c [s] ff ff
l6563 - l6563a application information 21/39 6.4 thd optimizer circuit the l6563/a is provided with a special circuit that reduces the conduction dead-angle occurring to the ac input current near the zero-crossings of the line voltage (crossover distortion). in this way the thd (total harmonic distortion) of the current is considerably reduced. a major cause of this distortion is the inability of the system to transfer energy effectively when the instantaneous line voltage is very low. this effect is magnified by the high- frequency filter capacitor placed after the bridge rectifier, which retains some residual voltage that causes the diodes of the bridge rectifier to be reverse-biased and the input current flow to temporarily stop. to overcome this issue the device forces the pfc pre-regulator to process more energy near the line voltage zero-crossings as compared to that commanded by the control loop. this will result in both minimizing the time interval where energy transfer is lacking and fully discharging the high-frequency filter capacitor after the bridge. figure 37 shows the internal block diagram of the thd optimizer circuit. figure 37. thd optimizer circuit + + mult comp t @ vac1 @ vac2 > vac1 t t to pwm comparator multiplier offset generator t vff 1 / v 2 t t + + mult comp t @ vac1 @ vac2 > vac1 t t to pwm comparator multiplier multiplier offset generator offset generator t vff 1 / v 2 1 / v 2 t t
application information l6563 - l6563a 22/39 figure 38. thd optimization: standard tm pfc controller (left side) and l6563/a (right side) essentially, the circuit artificially increases the on-time of the power switch with a positive offset added to the output of the multiplier in the proximity of the line voltage zero-crossings. this offset is reduced as the instantaneous line voltage increases, so that it becomes negligible as the line voltage moves toward the top of the sinusoid. furthermore the offset is modulated by the voltage on the v ff pin (see section 6.3 on page 18 section) so as to have little offset at low line, where energy transfer at zero crossings is typically quite good, and a larger offset at high line where the energy transfer gets worse. the effect of the circuit is shown in figure 38 , where the key waveforms of a standard tm pfc controller are compared to those of this chip. to take maximum benefit from the thd optimizer circuit, the high-frequency filter capacitor after the bridge rectifier should be minimized, compatibly with emi filtering needs. a large capacitance, in fact, introduces a conduction dead-angle of the ac input current in itself - even with an ideal energy transfer by the pfc pre-regulator - thus reducing the effectiveness of the optimizer circuit. imains vdrain imains vdrain input current input current mosfet's drain voltage mosfet's drain voltage rectified mains voltage rectified mains voltage input current input current
l6563 - l6563a application information 23/39 6.5 tracking boost function in some applications it may be advantageous to regulate the output voltage of the pfc pre- regulator so that it tracks the rms input vo ltage rather than at a fixed value like in conventional boost pre-regulators. this is commonly referred to as "tracking boost" or "follower boost" approach. with this ic the function can be realized by connecting a resistor (r t ) between the tbo pin and ground. the tbo pin presents a dc level equal to the peak of the mult pin voltage and is then representative of the mains rms voltage. the resistor defines a current, equal to v(tbo)/r t , that is internally 1:1 mirrored and sunk from pin inv (pin 1) input of the error amplifier. in this way, when the mains voltage increases t he voltage at tbo pin will increase as well and so will do the curren t flowing through th e resistor connecte d between tbo and gnd. then a larger current will be sunk by in v pin and the ou tput voltage of the pfc pre- regulator will be forc ed to get higher. obviously, the out put voltage will move in the opposite direction if the input voltage decreases. to avoid undesired output voltage rise should the mains voltage exceed the maximum specified value, the voltage at the tbo pin is clamped at 3v. by properly selecting the multiplier bias it is possible to set the ma ximum input voltage above which input-to-output tracking ends and the output voltage becomes constant. if this function is not used, leave the pin open: the device will regulate a fixed output voltage. starting from the following data: vin 1 = minimum specified input rms voltage; vin 2 = maximum specified input rms voltage; vo 1 = regulated output voltage @ vin = vin 1 ; vo 2 = regulated output voltage @ vin = vin 2 ; vox = absolute maximum limit for the regulated output voltage; ? vo = ovp threshold,
application information l6563 - l6563a 24/39 to set the output voltage at the desired values use the following design procedure: 1. determine the input rms voltage vin clamp that produces vo = vox: equation 6 and choose a value vin x such that vin 2 = vin x < vin clamp . this will result in a limitation of the output voltage range below vox (i t will equal vox if one chooses vin x = vin clamp ) 2. determine the divider ratio of the mult pin (pin 3) bias: equation 7 and check that at minimum mains voltage vin 1 the peak voltage on pin 3 is greater than 0.65v. 3. determine r1, the upper resistor of the output divider: equation 8 4. calculate the lower resistor r 2 of the output divider and the adjustment resistor r t : equation 9 vin clamp vox vo 1 ? vo 2 vo 1 ? --------------------------- vin 2 vox vo 2 ? vo 2 vo 1 ? --------------------------- vin 1 ? ? ? = k 3 2vin x ? ----------------------- = r1 vo ? 20 ---------- - 10 6 ? = r2 2.5 r1 vin 2 vin 1 ? vo 1 2.5 ? () vin 2 vo 2 2.5 ? () vin 1 ? ? ? -------------------------------------------------------------------------------------------------- ? ? = r t 2kr1 vin 2 vin 1 ? vo 2 vo 1 ? ----------------------------- - ?? ? =
l6563 - l6563a application information 25/39 5. check that the maximum current sourced by the tbo pin (pin 6) does not exceed the maximum specified (0.25ma): equation 10 in the following mathcad? sheet, as an example, the calculation is shown for the circuit illustrated in figure 40 . figure 41 shows the internal block diagram of the tracking boost function. design data vin 1 := 88v vo 1 := 200v vin 2 := 264v vo 2 := 385v vox ;= 400v ? vo ;= 40v step 1 choose: vin x : = 270v step 2 step 3 i tbomax 3 r t ------ - 0.25 10 3 ? ? = vin clamp : vox vo 1 ? vo 2 vo 1 ? --------------------------- vin 2 ? = vox vo 2 ? vo 2 vo 1 ? --------------------------- vin 1 ? ? vin clamp = 278.27v k: 3 2vin x ? ----------------------- = k = 7.857 x 10 -3 r1: vo ? 20 ---------- - 10 6 ? = r1 = 2 x 10 6 ?
application information l6563 - l6563a 26/39 step 4 step 5 figure 39. output voltage vs. input voltage characteristic with tbo r2: 2.5 r1 vin 2 vin 1 ? vo 1 2.5 ? () vin 2 vo 2 2.5 ? () vin 1 ? ? ? -------------------------------------------------------------------------------------------------- ? ? = r2 = 4.762 x 10 4 ? r t :k2r1 vin 2 vin 1 ? vo 2 vo 1 ? ----------------------------- - ??? = r t = 2.114 x 10 4 ? i tbomax : 3 r t ------ - 10 3 ? = i tbomax = 0.142 ma v multpk k2vi ?? vo(vin 1 ) = 200v vo(vi): = v tbo if v multpk 3,v multpk ,3 < () vo(vin 2 ) = 385v 2.5 1 r1 r2 ------- - + ?? ?? v tbo r1 r t ------- - ? + ? vo(vin x ) = 391.307v 100 150 200 250 300 200 250 300 350 400 vo 2 vo vin ( ) vin 2 vin x vin
l6563 - l6563a application information 27/39 6.6 inductor saturation detection (l6563 only) boost inductor's hard saturation may be a fatal event for a pfc pre-regulator: the current upslope becomes so large (50-100 times steeper, see figure 42 ) that during the current sense propagation delay the current may reach abnormally high values. the voltage drop caused by this abnormal current on the sense resistor reduces the gate-to-source voltage, so that the mosfet may work in the active region and dissipate a huge amount of power, which leads to a catastrophic failu re after few switching cycles. however, in some applications such as ac-dc adapters, where the pfc pre-regulator is turned off at light load for energy saving reasons, even a well-designed boost inductor may occasionally slightly saturate when the pfc stage is restarted because of a larger load demand. this happens when the restart occurs at an unfavorable line voltage phase, so that the output voltage may drop significantly below the rectified peak voltage. as a result, in the figure 40. 80w, wide-range-mains pfc pre-regul ator with tracking boost function active 14 3 bridge 4 x 1n4007 c1 0.22 f 400v c3 22 m f 25v fuse 4a/250v r3 68 k ? t 11 12 l6563 13 2 1 c6 100 nf r6 10 ? mos stp8nm50 4 c6 56 f 400v vo=200 to 385 v po=80w vac (88v to 264v) r7a,b 0.68 ? 1/4 w r9 47.5 k ? + - c2 2.2nf d1 stth1l06 ntc r5 62 k ? c5 1 f 5 c4 470 nf 6 7 10 8 9 r4 21 k ? r8b 1 m ? supply voltage 10.3 to 22v r8a 1 m ? c7 10 nf r10b 3.3 m ? r10a 3.3 m ? r11 34.8 k ? r1b 3.3 m ? r1a 3.3 m ? r2 51.1 k ? r10 390 k ? figure 41. tracking boost and voltage feedforward blocks r1 l6563 l6563a inv 1 vout tbo 6 1:1 current mirror r t 2.5v e/a + - comp 2 3v - + 5 i tbo i r1 mult 3 r5 rectified mains r6 "ideal" diode multiplier 1/v 2 current reference r2 i r2 i tbo 9.5v 9.5v vff c ff r ff
application information l6563 - l6563a 28/39 boost inductor the inrush current coming from the bridge rectifier adds up to the switched current and, furthermore, there is little or no voltage available for demagnetization. to cope with a saturated inductor, the l6563 is provided with a second comparator on the current sense pin (cs, pin 4) that stops and latches off the ic if the voltage, normally limited within 1.1v, exceeds 1.7v. also the cascaded dc-dc converter can be stopped via the pwm_latch pin that is asserted high. in this way the entire system is stopped and enabled to restart only after recycling the input power, that is when the vcc voltages of the l6563 and the pwm controller go below their respective uvlo thresh olds. system safety will be considerably increased. to better suit the applications where a certain level of saturation of the boost inductor needs to be tolerated, the l6563a does not support this protection function. 6.7 power management/housekeeping functions a special feature of this ic is that it fac ilitates the implementation of the "housekeeping" circuitry needed to coordinate the operation of the pfc stage to that of the cascaded dc- dc converter. the functions realized by the housekeeping circuitry ensure that transient conditions like power-up or power down sequencing or failures of either power stage be properly handled. this device provides some pins to do that. as already mentioned, one communication line between the ic and the pwm controller of the cascaded dc-dc converter is the pwm_latch pin, which is normally open when th e pfc works properly and goes high if it loses control of the output voltage (because of a failure of the control loop) or if the boost inductor saturates, with the aim of latching off the pwm controller of the cascaded dc-dc converter as well ( section 6.2: feedback failure protection (ffp) on page 18 for more details). a second communication line can be established via the disable function included in the pfc_ok pin ( section 6.2 on page 18 for more details ). typically this line is used to allow the pwm controller of the cascaded dc-dc converter to shut down the l6563/a in case of light load, to minimize the no-load input cons umption. should the residual consumption of the chip be an issue, it is also possible to cut down the supply voltage. interface circuits like those shown in figure 43 , where the l6563/a works along with the l5991, pwm controller with standby function, can be used. needless to say, this operation assumes that the cascaded dc-dc converter stage works as the ma ster and the pfc stage as the slave or, in other words, that the dc-dc stage starts first, it powers both controllers and enables/disables the operation of the pfc stage. figure 42. effect of boost inductor saturation on the mosfet current and detection method
l6563 - l6563a application information 29/39 the third communication line is the pwm_stop pin (pin 9), which works in conjunction with the run pin (pin 10). the purpose of the pwm_stop pin is to inhibit the pwm activity of both the pfc stage and the cascaded dc-dc converter. the pin is an open collector, normally open, that goes low if the device is disabled by a voltage lower than 0.52v on the run pin. it is important to point out that this function works correctly in systems where the pfc stage is the master and the cascaded dc-dc converter is the slave or, in other words, where the pfc stage starts first, powers both controllers and enables/disables the operation of the dc-dc stage. this function is quite flexible and can be used in different ways. in systems comprising an auxiliary converter and a main converter (e.g. desktop pc's silver bo x or hi-end lcd-tv), where the auxiliary converter also powers the co ntrollers of the main converter, the pin run can be used to start and stop the main converter. in the simplest case, to enable/disable the pwm controller the pwm_stop pin can be connected to either the output of the error amplifier ( figure 44 a ) or, if the chip is provided wi th it, to its soft-start pin ( figure 44 b ). the use of the soft-start pin allows the designer to delay the start-up of the dc-dc stage with respect to that of the pfc stage, which is often desired. an underlying assumption in order for that to work properly is that the uvlo thresholds of the pwm controller are certainly higher than those of the l6563/a. figure 43. interface circuits that let dc-dc converter?s controller ic disable the l6563/a at light load l5991/a st-by 4 16 27 k ? vref l6563 pfc_ok 7 100 k ? 150 k ? 150 k ? 47 k ? 100 nf bc547 bc547 bc557 l5991/a st-by 4 16 27 k ? vref l6563 vcc 14 100 k ? 150 k ? 150 k ? 15 k ? 100 nf bc557 bc547 bc557 100 nf supply_bus l6668 pfc_stop 14 16 vcc 10 k ? bc557 2.2 k ? l6563 l6563a vcc 14 8.2 v l6563 l6563a (run) pfc_ok bc547 l6668 14 pfc_stop 7 (10) 2.2 k ? 8 vref 100 k ? l6599 pfc_stop 14 l6563 l6563a (run) pfc_ok 7 (10)
application information l6563 - l6563a 30/39 figure 44. interface circuits that let the l6563/a switch on or off a pwm controller if this is not the case or it is not possible to achieve a start-up delay long enough (because this prevents the dc-dc stage from starting up correctly) or, simply, the pwm controller is devoid of soft start, the arrangement of figure 45 lets the dc-dc converter start-up when the voltage generated by the pfc stage reaches a preset value. the technique relies on the uvlo thresholds of the pwm controller. figure 45. interface circuits for actual power-up sequencing (master pfc) another possible use of the run and pwm_stop pins (again, in systems where the pfc stage is the master) is brownout protection, thanks to the hysteresis provided. brownout protection is basically a not-latched device shutdown function that must be activated when a condition of mains undervoltage is detected. this condition may cause overheating of the primary power section due to an excess of rms current. brownout can also cause the pfc pre-regulator to work open loop and this could be dangerous to the pfc stage itself and the downstream converter, should the input voltage return abruptly to its rated value. another problem is the spurious restarts that may occur during converter power down and that cause the output voltage of the converter not to decay to zero monotonically. for these reasons it is usually preferable to shutdown the unit in case of brownout.
l6563 - l6563a application information 31/39 ic shutdown upon brownout can be easily realized as shown in figure 46 the scheme on the left is of general use, the one on the right can be used if the bias levels of the multiplier and the r ff c ff time constant are compatible with the specified brownout level and with the specified holdup time respectively. in ta b l e 6 it is possible to find a summary of a ll of the above mentioned working conditions that cause the device to stop operating. figure 46. brownout protection (master pfc) 6.8 summary of l6563/a idle states . 10 run ac mains l6563 l6563a vff l6563 l6563a 5 run 10 r ff c ff table 6. summary of l6563/a idle states condition caused or revealed by pwm_latch (pin 8) pwm_stop (pin 9) typical ic consumption ic behavior uvlo vcc < 8.7 v open open 50 a auto-restart feedback disconnected pfc_ok > 2.5 v active (high) open 180 a latched saturated boost inductor vcs > 1.7 v (l6563 only) active (high) (l6563 only) open 180 a (l6563 only) latched (l6563 only) ac brownout run < 0.52 v open active (low) 1.5 ma auto-restart standby pfc_ok < 0.2 v open open 1.5 ma auto-restart
application examples and ideas l6563 - l6563a 32/39 7 application examples and ideas figure 47. demo board (eval6563-80w) 80w, wide-range, tracking boost: electrical schematic boost inductor spec: e25x13x7 core, 3c85 ferrite or equivalent 1.6 mm gap for 0.43 mh primary inductance primary: 80 turns 20 x 0.1 mm secondary: 9 turns 0.1 mm 14 3 p1 1w08g r11a 1 m ? c1 0.47 f 400v c2 33 f 25v fuse 4a/250v r3a 120 k ? d3 1n4148 d2 20 v r2 33 ? 15 nf c6 r1 47 k ? t 11 12 l6563 13 2 1 c12 220 nf r6 22 ? q1 stp8nm50 4 c5 56 f 400 v vo=220 to 390 v po = 80 w vac (88v to 264v) r8 37.4 k ? + - c7 4.7 nf d1 stth2l06 ntc 2.5 ? r4 39 k ? c8 1 f 5 c9 470 nf 6 7 10 8 9 r14 22.1 k ? r13 10.5 k ? r3b 120 k ? r11b 1 m ? r10 15.8 k ? r9a 1 m ? r9b 1 m ? r12a 1 m ? r12a 1 m ? r7a 0.68 ? 1/2 w r7b 0.68 ? 1/2 w r15 0 ? c10 n.a. r17 390 k ? c11 4.7 nf r18 47 k ? r20 47 k ? tp1 tp2 daux 1n4007 c4 100 nf figure 48. eval6563-80w: pcb and component layout (top view, real size: 64 x 94 mm)
l6563 - l6563a application examples and ideas 33/39 figure 49. eval6563-80w: pcb layout, soldering side (top view) note: measurements done with the line filter shown in figure 51. note: measurements done with the line filter shown in figure 51. table 7. eval6563-80w: evaluation results at full load vin (v ac ) pin (w) vo (v dc ) ? vo (v pk-pk ) po (w) (%) pf thd (%) 90 85.3 219.4 16.6 79.64 93.4 0.999 3.7 115 84.9 244.1 15.0 80.80 95.2 0.998 4.3 135 83.7 263.7 13.9 80.16 95.8 0.997 4.8 180 83.5 307.6 14.5 80.28 96.1 0.993 6.0 230 85.2 356.7 13.0 81.33 95.5 0.984 7.7 265 85.0 390.6 12.1 80.85 95.1 0.974 9.5 table 8. eval6563-80w: evaluation results at half load vin (v ac ) pin (w) vo (v dc ) ? vo (v pk-pk ) po (w) (%) pf thd (%) 90 43.4 219.9 8.6 40.90 94.2 0.997 4.8 115 42.6 244.5 7.7 40.10 94.1 0.994 5.7 135 43.1 264.0 7.3 40.39 93.7 0.989 6.5 180 43.8 307.7 7.7 40.31 92.0 0.978 8.4 230 45.6 356.8 6.8 41.03 90.0 0.951 9.6 265 46.0 390.7 6.7 40.63 88.3 0.920 14.2
application examples and ideas l6563 - l6563a 34/39 figure 50. eval6563-80w: vout vs. vin relationship (tracking boost) figure 51. line filter (not tested for emi compliance) used for eval6563-80w evaluation
l6563 - l6563a application examples and ideas 35/39 figure 52. 250w, wide-range-mains pfc pre-regulator with fixed output voltage 14 3 b1 kbu8m r1a 820 k c1 1 f 400v c2 1 f fuse 8a/250v r3 47 k 11 12 l6563 13 21 m1 stp12nm50 4 r9a 1 m c8 150 f 450 v vout = 400v pout = 250 w vac 88v to 264v r8a,b 0.22 1 w r10 12.7 k + - c3 10nf d2 stth5l06 r6 33 c4 1 f r1b 820 k r2 10 k d3 1n4148 r9b 1 m ntc1 2.5 d1 1n5406 c6 470 nf 630 v r5 6.8 k l1 r4 1 m vcc 10.3 to 22 v r11a 1.87 m r12 20 k r11b 1.87 m 6 7 5 r7 390 k c5 470nf 8 9 c7 10 nf 10 boost inductor (l1) spec etd29x16x10 core, 3c85 ferrite or equivalent 1.5 mm gap for 150 h primary inductance primary: 74 turns 20xawg30 ( 0.3 mm) secondar y : 8 turns 0.1 mm figure 53. 350w, wide-range-mains pfc pre-regulator with fixed output voltage and fot control 14 3 b1 kbu8m r1a 620 k c1 1 f 400v c2 1 f fuse 8a/250v r8 1.5 k 11 12 l6563 13 21 m1a stp12nm50 4 c11 220 f 450 v vout = 400v pout = 350w vac 88v to 264v r12a,b,c 0.33 1 w + - c3 10nf d2 stth806dti r9 6.8 c5 1 f r1b 620 k r2 10 k d3 1n4148 d5 1n4148 r7 12 k c7 560 pf c6 330 pf ntc1 2.5 d1 1n5406 c9 470 nf 630 v r5 6.8 k r10 6.8 d4 1n4148 m1b stp12nm50 r6 1.5 k tr1 bc557 l1 r15a 1.87 m r16 20 k r15b 1.87 m 6 7 5 r3 390 k c4 470nf 9 8 9 c10 10 nf 10 c8 330 pf r11 330 r13a 1 m r14 12.7 k r13b 1 m r4 1 m vcc 10.3 to 22 v l1: core e42*21*15, b2 material 1.9 mm air gap on centre leg, main winding inductance 0.55 mh 58 t of 20 x awg32 ( 0.2 mm)
application examples and ideas l6563 - l6563a 36/39 figure 54. demagnetization sensing without auxiliary winding figure 55. enhanced turn-off for big mosfet driving v inac l6563 l6563a v out c zcd r zcd r load 9 zcd 13 12 14 gd gnd driver v cc q l6563 l6563a rs bc327
l6563 - l6563a package mechanical data 37/39 8 package mechanical data in order to meet environmental requirements, st offers these devices in ecopack? packages. these packages have a lead-free second level interconnect . the category of second level interconnect is marked on the package and on the inner box label, in compliance with jedec standard jesd97. the maximum ratings related to soldering conditions are also marked on the inner box label. ecopack is an st trademark. ecopack specifications are available at: www.st.com table 9. so-14 mechanical data dim. mm. inch min typ max min typ max a 1.35 1.75 0.053 0.069 a1 0.10 0.30 0.004 0.012 a2 1.10 1.65 0.043 0.065 b 0.33 0.51 0.013 0.020 c 0.19 0.25 0.007 0.01 d (1) 8.55 8.75 0.337 0.344 e 3.80 4.0 0.150 0.157 e 1.27 0.050 h 5.8 6.20 0.228 0.244 h 0.25 0.50 0.01 0.02 l 0.40 1.27 0.016 0.050 k 0 (min.), 8 (max.) ddd 0.10 0.004 figure 56. package dimensions 0016019d
revision history l6563 - l6563a 38/39 9 revision history table 10. revision history date revision changes 13-nov-2004 1 first issue 24-sep-2005 2 changed the maturity from ?preliminary data? to ?datasheet? 17-nov-2006 3 added new part number l6563a ( table 2 ) updated the section 4 on page 7 & section 7 on page 32 the document has been reformatted 12-mar-2007 4 replaced block diagram, added figure 37 on page 21 and minor editor changes.
l6563 - l6563a 39/39 please read carefully: information in this document is provided solely in connection with st products. stmicroelectronics nv and its subsidiaries (?st ?) reserve the right to make changes, corrections, modifications or improvements, to this document, and the products and services described he rein at any time, without notice. all st products are sold pursuant to st?s terms and conditions of sale. purchasers are solely responsible for the choice, selection and use of the st products and services described herein, and st as sumes no liability whatsoever relating to the choice, selection or use of the st products and services described herein. no license, express or implied, by estoppel or otherwise, to any intellectual property rights is granted under this document. i f any part of this document refers to any third party products or services it shall not be deemed a license grant by st for the use of such third party products or services, or any intellectual property contained therein or considered as a warranty covering the use in any manner whatsoev er of such third party products or services or any intellectual property contained therein. unless otherwise set forth in st?s terms and conditions of sale st disclaims any express or implied warranty with respect to the use and/or sale of st products including without limitation implied warranties of merchantability, fitness for a parti cular purpose (and their equivalents under the laws of any jurisdiction), or infringement of any patent, copyright or other intellectual property right. unless expressly approved in writing by an authorized st representative, st products are not recommended, authorized or warranted for use in milita ry, air craft, space, life saving, or life sustaining applications, nor in products or systems where failure or malfunction may result in personal injury, death, or severe property or environmental damage. st products which are not specified as "automotive grade" may only be used in automotive applications at user?s own risk. resale of st products with provisions different from the statements and/or technical features set forth in this document shall immediately void any warranty granted by st for the st product or service described herein and shall not create or extend in any manner whatsoev er, any liability of st. st and the st logo are trademarks or registered trademarks of st in various countries. information in this document supersedes and replaces all information previously supplied. the st logo is a registered trademark of stmicroelectronics. all other names are the property of their respective owners. ? 2007 stmicroelectronics - all rights reserved stmicroelectronics group of companies australia - belgium - brazil - canada - china - czech republic - finland - france - germany - hong kong - india - israel - ital y - japan - malaysia - malta - morocco - singapore - spain - sweden - switzerland - united kingdom - united states of america www.st.com

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